This invention relates to a stacked-type semiconductor package, and more particularly to a stacked-type DRAM package which has high data rate transfer capability.
To increase memory capacity of a memory device package without making its profile large, there have been employed multiple techniques for stacking a plurality of memory chips into a vertical chip stack. For example, known techniques are disclosed in JP-A H11-220088 and U.S. Pat. No. 6,473,308 B2, which are incorporated herein by reference in its entirety. JP-A H11-220088 provides a stackable chip package of a unique structure, in accordance with which a chip stack can be obtained simply by stacking the same structured packages in turn. U.S. Pat. No. 6,473,308 B2 provides a chip package including a flex circuit which allows multiple chip packages to be easily assembled into a chip stack. However, according to the above prior arts, stacked packages in a chip stack have different electric lengths of data paths.
To solve the problem of the different electric lengths on stacked packages, US 2004/0227222 A1 has disclosed a four-layer substrate or tape comprising four conductive layers, which provides almost the same electric lengths to semiconductor chips mounted on the opposite surfaces of the tape. However, the four-layer tape is more expensive than a two-layer tape of normal one and increases a cost of a staked-type semiconductor package.
Therefore, there is a need for another technique of a staked-type semiconductor package which allows electric lengths of packages to be substantially equal to each other.